[memory architecture and method for repairing a serial access memory]

ABSTRACT

A memory architecture and method for repairing a serial access memory is disclosed. The memory architecture has a main memory unit and a redundant memory unit made from an independent memory module. The memory architecture further incorporates other circuits including a data selection unit, a fuse box, a comparable logic unit and a pointer control unit. The comparable logic unit uses a first-in-first-out scheme to access serial data to simplify the circuit. Thus, the invention has lower production costs and greater design flexibility.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the priority benefit of Taiwanapplication serial no.91120412, filed on Sep. 9, 2002.

BACKGROUND OF INVENTION

[0002] 1. Field of Invention

[0003] The present invention relates to a memory architecture and methodfor repairing a serial access memory. More particularly, the presentinvention relates to a memory architecture and method for repairing aserial access memory by providing a control interface circuit andredundant memory.

[0004] 2. Description of Related Art

[0005] Following recent advances in electronic technology, informationexchange between users is increasingly frequent. Information exchangeoften requires a large storage medium to hold data. As the access speedof memory has increased, so memory has become an important storagemedium in information systems. Due to a rapid increase in the volume oftransmitted data, memory with higher access speed and increased storagecapacity is in great demand. To increase the production yield of memoryand hence reduce production costs, especially for application specificintegrated circuit (ASIC) devices, whose overall yield is greatlyaffected by the corresponding yield of its memory module, a type ofmemory module with repairing capacity has been developed. This type ofthe memory module often includes a main memory as well as a redundantmemory and peripheral control circuits. The redundant memory can be usedto replace a portion of some damaged memory cells inside the mainmemory.

[0006]FIG. 1 is a block diagram showing various components inside aconventional memory module 100 with repairing capability. As shown inFIG. 1, aside from having a main memory 110, the memory module 100 alsohas a redundant memory 120 and peripheral control circuits, including afuse box 130, a comparable logic unit 140, and a routing logic unit 150,as shown in FIG. 1. If a portion of the memory cells inside the mainmemory 110 is damaged, corresponding memory cells in the redundantmemory 120 can be used to replace these damaged memory cells.

[0007] First, the addresses of the damaged memory cells inside the mainmemory 110 are registered. Thereafter, fuses inside a fuse box 130,corresponding to the addresses of these damaged memory cells, are cutoff by the use of a laser, in order to register these addresses in thefuse box 130. Before accessing the memory module 100 with repairingcapacity, the comparable logic unit 140 compares access memory address Awith all registered addresses of the damaged memory cells inside thefuse box 130. If one of the addresses of the damaged memory cell matchesthe access memory address A, the comparable logic unit 140 outputs arepair signal R, indicating that access memory address A is one of theregistered addresses of the damaged memory cells and the repair signal Ris sent to routing logic unit 150. The routing logic unit 150 thenswitches an accessing pathway from the damaged memory cell correspondingto access memory address A within the main memory 110 to an address inthe redundant memory 120 that corresponds to access memory address A.

[0008]FIG. 2 is an example of one registered unit of a conventional fusebox, in which fuses and a comparable circuit for registering the damagedmemory addresses are provided. In the example, each address of thedamaged memory cell is an 8-bit byte. Hence, there are altogether 16fuses including F0˜F7 and F0B˜F7B as well as 16 correspondingtransistors including N0˜N7 and N0B˜N7B for each address of the damagedmemory cell. The fuse box in FIG. 2 also includes a load L and aninverter 210 for outputting a repair signal R1 that indicates theaccessed address is the address of a damaged memory cell. The drainterminals of the transistors N0˜N7B are connected to an operatingvoltage source VDD through their respective fuses F0˜F7B, while thesource terminals of the transistors N0˜N7B are connected to the load L.The gate terminals of the transistors N0˜N7 are connected to respectivebits A0˜A7 of the access memory address. Similarly, the gate terminalsof the transistors N0B˜N7B are connected to respectively bits A0B˜A7B ofthe access memory address.

[0009] Assuming the memory cell in the main memory 110 has an addressfrom a low bit to a high bit is 00010001 and is a damaged memory cell, alaser can be used to cut off the fuse F0B, F1B, F2B, F3, F4B, F5B, F6Band F7. The address of the damaged memory cell “00010001” is thenregistered in the fuse box. When the bits A0˜A7 of the access memoryaddress A are 00010001, that is, identical to the address of the damagedmemory cell, the gates of the uncut fuse of the transistors N0, N1, N2,N3B, N4, N5, N6 and N7B are applied with a low voltage potential and notturned on. Hence, the repair signal terminal R1 output from the fuse boxpossesses a high voltage potential. When the bits A0˜A7 of the accessmemory address A are not the registered address “00010001” in the fusebox, the repair signal terminal R1 output from the fuse box is in a lowvoltage potential. Through such a mechanism, the status, i.e. damaged ornot damaged, the memory cell of a requested access memory address isindicated. Obviously, if the number of damaged memory addresses that canbe held within the fuse box 130 is greater than one, the circuit in FIG.2 must be correspondingly expanded.

[0010] When the aforementioned memory module 100 with repairing capacityis applied to an ASIC device that operates in first-in-first-out (FIFO)serial data accessing mode, the following disadvantages are apparent inthe conventional architecture: 1. The comparable logic unit 140 needs tocompare the access memory address with all the addresses of the damagedmemory cells registered by the fuse box 130. Hence, the comparable logiccircuit 140 is typically complicated and consumes a lot of power. 2.Since the access pathway is changed through the addressing logic unit150 only after the comparable logic unit 140 receives the access memoryaddress and compares it with all the addresses of damaged memory cellsregistered by the fuse box 130, access performance for the memory module100 is restricted. 3. ASIC design that uses a memory module 100 withrepairing capacity is normally developed by using a memory cell librarycontaining programs written for a memory design having embeddedrepairing functions. As such, the development time for an ASIC designpossessing a memory module 100 with repairing capacity is usually longerthan for an ASIC design that has a memory module 100 without repairingcapacity. In addition, such ASIC designs possessing a memory module 100with repairing capacity are relatively less flexible than those withoutrepairing capacity. Furthermore, ASIC designs that have memory modules100 without repairing capacity are much easier to be obtained in theart, as opposed to those with repairing capacity, which reduces the workand costs involved in such designs.

SUMMARY OF INVENTION

[0011] Accordingly, one object of the present invention is to provide amemory architecture and method for repairing a serial access memory. Ascompared with the conventional memory modules in integrated circuitdevices, the comparable logic unit used in the memory module accordingto the present invention is simplified. Also the present invention isnot required to compare an access memory address with all the addressesof the damaged memory cells. In addition, the development time,flexibility of applications, efforts and costs for the integratedcircuit design are significantly improved.

[0012] One further object of the present invention is to provide amemory architecture and method for repairing serial access memory. Thememory module is implemented by a standard memory module design withouta repair function, which is easily found in a cell library. In analternative embodiment of the invention, the mechanism is used in anapplication specific integrated circuit (ASIC) device. A controlinterface circuit and redundant memory are further provided in thememory module to implement the repair function for the memory module inthe integrated circuit device.

[0013] To achieve these and other advantages and in accordance with thepurpose of the invention, as embodied and broadly described herein, theinvention provides an integrated circuit with an application circuit anda memory module. The memory module includes a main memory, a redundantmemory and a control interface circuit. The control interface circuit isused to store a plurality of addresses. Each of the addressescorresponds to a damaged memory cell in the main memory. When the memorymodule is accessed by an access address, the control interface circuitissues a pointer address to point to the corresponding address in thestored addresses in the control interface circuit and compares theaddress corresponding to the pointer address and the access address. Ifthe address corresponding to the pointer address is equal to the accessaddress, data accessed by the access address from the memory module isread out from the redundant memory, instead of the main memory.

[0014] In an alternative embodiment of the above-mentioned integratedcircuit, when the data accessed by the access address from the memorymodule is read out from the memory address of the redundant memory, thememory address corresponds to the pointer address issued by the controlinterface circuit.

[0015] In an alternative embodiment of the above-mentioned integratedcircuit, each of the addresses stored in the control interface circuithas a memory address that corresponds to the redundant memory. If theaddress corresponding to the pointer address is equal to the accessaddress, the data is read out from the memory address of the redundantmemory corresponding to the address.

[0016] In an alternative embodiment of the above-mentioned integratedcircuit, the control interface circuit comprises a pointer control unit,a fuse box and a comparable logic unit. The pointer control unit,coupled to the redundant memory, is used to generate the pointeraddress. The fuse box, coupled to the pointer control unit, is used toregister the addresses of the damaged cells of the main memory andoutput one of the addresses according to the pointer address. Thecomparable logic unit, coupled to the fuse box, is used to compare theaccess address with the address output from the fuse box, and generate aredundant selection signal if the address corresponding to the pointeraddress is equal to the access address. If the redundant selectionsignal is activated, the data accessed by the access address from thememory module is read out from the redundant memory, instead of the mainmemory.

[0017] The control interface circuit further includes a data selectionunit coupled to the application circuit, a main memory, redundant memoryand a comparable logic unit. If the redundant selection signal isactivated, the data accessed by the access address from the memorymodule is read out from the redundant memory. If the redundant selectionsignal is not activated, data accessed by the access address from thememory module is read out from the main memory.

[0018] The data selection unit includes a multiplexing circuit. Thecomparable logic unit includes an assembly of NOR gates.

[0019] In the above-mentioned integrated circuit, the pointer controlunit increments or decrements the pointer address by a step value whenthe redundant selection signal is set. In a preferred embodiment, thestep value is one.

[0020] To realize these and other advantages and in accordance with thepurpose of the invention, as embodied and broadly described herein, theinvention provides a method for an integrated circuit with anapplication circuit and a memory module. The memory module includes amain memory, a redundant memory and a control interface circuit. Thecontrol interface circuit is used to store a plurality of addresses,each of which corresponds to a damaged memory cell in the main memory.The method includes assessing the memory module by an access address,issuing a pointer address through the control interface circuit to pointto a corresponding stored addresses in the control interface circuit,comparing the address corresponding to the pointer address and theaccess address. If the address corresponding to the pointer address isequal to the access address, data accessed by the access address fromthe memory module is read out from the redundant memory.

[0021] In an alternative embodiment, in the above-mentioned method forintegrated circuits, the memory address corresponds to the pointeraddress issued by the control interface circuit.

[0022] In an alternative embodiment, in the above-mentioned method forthe integrated circuit, if the redundant selection signal is activated,the data accessed by the access address from the memory module is readout from the redundant memory, if the redundant selection signal is notactivated, data accessed by the access address from the memory module isread out from the main memory.

[0023] In an alternative embodiment, in the above-mentioned method forthe integrated circuit, the pointer address is incremented ordecremented by a step value when the redundant selection signal is set.The step value is, for example, one.

[0024] It is to be understood that both the foregoing generaldescription and the following detailed description are exemplary, andintended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF DRAWINGS

[0025] The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitutepart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

[0026]FIG. 1 is a block diagram showing various components inside aconventional memory with fault-repairing capability.

[0027]FIG. 2 is an example of a conventional system with a fuse link andcomparable circuit registering damaged memory addresses.

[0028]FIG. 3 is a block diagram of a memory structure withfault-repairing capability according to one preferred embodiment of thisinvention.

DETAILED DESCRIPTION

[0029] Reference will now be made in detail to the present preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings. Wherever possible, the same reference numbers areused in the drawings and the description to refer to the same or likeparts.

[0030] The invention provides a memory architecture and method forrepairing a serial access memory. The memory module is implemented by astandard memory module design without a repair function, easily foundand obtained in a cell library provided by some resources without anycost. In an alternative embodiment of the invention, the mechanism isused in an application specific integrated circuit (ASIC) design havinga memory module design without repair function. A control interfacecircuit and a redundant memory are further provided in the memory moduleto implement the repair function for the memory module in the ASICdevice.

[0031] As compared with conventional memory modules in integratedcircuit devices, the comparable logic unit used in the memory module ofthe preferred embodiment is simplified. The access memory address doesnot have to be compared with all the addresses of the damaged memorycells registered by the fuse box. Hence, the comparable logic circuitoccupies a relatively lower layout area and consumes less power than aconventional comparable logic unit. In addition, since the memory moduleis implemented by a standard memory module design without a repairfunction, the development time, flexibility of applications and effortcosts of the integrated circuit design are significantly improved.

[0032] An ASIC device is explained in the following embodimentaccompanying the corresponding drawing. However, it is apparent to thoseskilled in the art that other kinds of integrated circuits can be madewith the mechanism of the present invention without departing from thescope or spirit of the invention.

[0033] Refer to FIG. 3, which shows block diagrams of an ASIC device 300of a preferred embodiment for the present invention. The ASIC device 300includes an application circuit 310 and a main memory 320, which is anembedded memory of a memory module for the ASIC device 300. The design305 for the ASIC device 300 includes an application circuit 310 and amain memory 320 without a repair function that can be easily found andobtained in a cell library provided by some resources with minimal cost.A redundant memory 340 and a control interface circuit 350 are furtherprovided to implement the repair function in the ASIC device 300. Thatis, in the preferred embodiment of the invention, the repair function iscompleted by such a mechanism including the redundant memory 340 and acontrol interface circuit 350. A memory module in the ASIC device 300includes the main memory 320, the redundant memory 340 and the controlinterface circuit 350.

[0034] The control interface circuit 350 includes a fuse box 352, acomparable logic unit 354, a pointer control unit 356 and a dataselection unit 358. The control interface circuit 350 is implemented byfull CMOS process design, which significantly reduces power consumptionduring operation. On the other hand, the prior art device is implementedby N CMOS design.

[0035] To reduce production costs, provide more design flexibility andboost overall performance, the ASIC device 300 does not use a designcell library with embedded repairing functions. In this invention, themain memory 320 and the redundant memory 340 are designed separately. Ingeneral, a design cell library with embedded repairing function needs toestablish a set of specifications before carrying out the design by anexternal institution. Hence, development time is usually long, theapplication program is usually inflexible and the design cost high. Onthe contrary, memory designs each without a repairing function but avariety of specifications are plentiful, easy to lay hold of and mostlyfree. Hence, using independent memory designs to serve as the mainmemory 320 and the redundant memory 340 and combining these with thecontrol interface circuit 350 in the embodiment, including the fuse box352, the comparable logic unit 354, the pointer control unit 356 and thedata selection unit 358, to form the ASIC device 300 not only lowersproduction costs, but also increases flexibility in providing the mainmemory 320 and the redundant memory 340 with a range of storagecapacity. This arrangement is especially useful for the ASIC device 300.

[0036] As shown in FIG. 3, the main memory 320 is used to accessserially transmitted data D according to accessing address A and theredundant memory 340 is used when a portion of memory cells in the mainmemory 320 are defective. In this case, the pointer control unit 356issues a memory address chosen by a pointer address P so that data Ddestined for the damaged memory cell is now stored inside the redundantmemory 340. Since the redundant memory 340 is only a backup memory forthe main memory 320, redundant memory 340 has a much lower storagecapacity than the main memory 320. In general, the ratio of memory cellsin the main memory 320 to the redundant memory 340 depends on actualrequirements. However, in order to be compatible with the number ofaddressed damaged memory cells in the main memory 320 registered insidethe fuse box 352, each of the addresses in the damaged memory cellsregistered inside the fuse box 352 corresponds to the address of amemory cell in the redundant memory 340. Consequently, the storagecapacity of the redundant memory 340 should at least match the number ofaddresses of the damaged memory cells inside the fuse box 352.

[0037] The main memory 320 preferably is a first-in-first-out (FIFO)serial data access memory. Due to the special data accessingcharacteristics of a FIFO serial data access memory system, thecomparable circuit inside the comparable logic unit 354 is very muchsimplified. For example, as compared to the comparable circuit used inthe circuit shown in FIG. 2, there is no need to compare all theregistered addresses of the damage memory cells inside the fuse box 352.Only the access address A picked up by the main memory 320 issequentially compared with the address B of one of the damaged memorycells picked up by the pointer address P issued by the pointer controlunit 356. To save power, in an alternative embodiment, the comparablelogic unit 354 is fabricated using an assembly of NOR gates. Since a NORgate only outputs a high potential when the value at both inputterminals is identical, NOR gates are particularly suitable for buildingcomparable circuits.

[0038] Assume the addresses of the damaged memory cells in the mainmemory 320 are the memory addresses A1, A2, A3 and A4 respectively. Whena laser is used to cut off the fuses inside the fuse box 352, the fouraddresses A1, A2, A3 and A4 must be sequentially stored inside the fusebox 352. Thereafter, the pointer control unit 356 outputs a pointeraddress P that points to an address for storing the address A1, so thatthe fuse box 352 is able to output the address B of the damaged memorycell equal to A1. The address A1 of the damaged memory cell is comparedwith the access address A via the comparable logic unit 354. If theaccess address A is found to be equal to A1, that is, the memory cellcorresponds to the access address A in the main memory 320 of an damagedmemory cell, the comparable logic unit 354, accordingly, generates aredundant selection signal S. The redundant selection signal S instructsdata selection unit 358 to divert a data accessing pathway from the mainmemory 320 to the redundant memory 340. Since the memory address of theredundant memory 340 is controlled by the output pointer address P ofthe pointer control unit 356, the redundant memory address pointed to bythe pointer address P replaces the damage memory address A1corresponding to the damaged memory cell in the main memory 320.

[0039] In addition, the pointer control unit 356 also receives theredundant selection signal S so that the pointer address P issequentially incremented or decremented by one step value. Preferably,the step value is one unit and points to the address in the fuse box 352where A2 is stored so that address B of another damaged memory celloutput from the fuse box 352 is equal to A2, which corresponds to theupdated pointer address P. Similarly, the address A2 of the damagedmemory cell is compared with the access address A through comparablelogic unit 354. If the access address A is found to be equal to A2, thatis, the memory cell that corresponds to access address A in the mainmemory 320 is a damaged memory cell, comparable logic unit 354 issues aredundant selection signal S. The redundant selection signal S informsthe data selection unit 358 so that the data access pathway isredirected to the redundant memory 340. Since the output pointer addressP of the pointer control unit 356 already points to the memory addressof the redundant memory 340 that corresponds to the address A2 of thedamaged memory cell, the memory address of the redundant memory 340actually replaces the memory address A2 of the damaged memory cell inthe main memory 320. Thereafter, the pointer address P is sequentiallyincremented or decremented by one step value so that the fuse box 352stores the addresses A3 and A4 as well as any corresponding addresses inthe redundant memory 340. Ultimately, the damaged cells inside the mainmemory 320 are sequentially repaired using corresponding redundantmemory addresses.

[0040] According to the setting of the redundant selection signal S, thedata selection unit 358 is able to select the correct data accesspathway between the main memory 320 and the redundant memory 340. Thedata selection unit 358 can be fabricated using a multiplexing ordemultiplexing multiplexer circuit. Obviously, the aforementionedembodiment uses an identical pointer address P to move the pointers thatpoint to the fuse box 352 and the redundant memory 340. However, this isnot the only selection. In practice, different pointer addresses may bechosen to move the pointer for the fuse box 352 and the redundant memory340 as long as one-to-one correspondence is always maintained.Furthermore, when different pointer addresses are used, the pointersneed not increment or decrement in synchrony. In other words, onepointer address may increment while another pointer address decrementsso long as a one-to-one correspondence relationship is maintained.

[0041] Accordingly, this invention has at least the followingadvantages: When the data access pathway needs to switch from the mainmemory 320 to the redundant memory 340, the accessing rate is fastbecause the pointer address P provided by the pointer control unit 356already points to a corresponding address in the redundant memory 340.Hence, access performance is greatly improved. In addition, since thecomparable logic unit 354 only has to compare the access memory addressand the addresses of the damaged memory cells in the fuse box 352sequentially, the comparable logic unit 354 can use a very simplecircuit design. Therefore, power consumption is reduced. Furthermore,because independent memory designs are used to form the main memory 320and the redundant memory 340, chipsets design cost is greatly reduced.In addition, since the capacity of the main memory 320 and redundantmemory 340 is scalable and the main memory 320 and redundant memory 340can be enabled to performing row or by column repairing, designflexibility is as a result increased.

[0042] It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncovers modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

1. A memory architecture used to repair a serial access memorycomprising a main memory, a redundant memory and a control interfacecircuit, the control interface circuit storing a plurality of addresses,each of the addresses corresponding to a damaged memory cell in the mainmemory, when the memory module is accessed by an access address, thecontrol interface circuit issuing a pointer address pointing to acorresponding address in the stored addresses in the control interfacecircuit and comparing the address corresponding to the pointer addressand the access address. If the address corresponding to the pointeraddress is equal to the access address, data accessed by the accessaddress from the memory module is read out from the redundant memory. 2.The memory architecture of claim 1, the data accessed by the accessaddress from the memory module being read out from a memory address ofthe redundant memory, the memory address corresponding to the pointeraddress issued by the control interface circuit.
 3. The memoryarchitecture of claim 1, each of the addresses stored in the controlinterface circuit having a memory address that corresponds to theredundant memory, if the address corresponding to the pointer address isequal to the access address, the data read out from the memory addressof the redundant memory corresponds to the address.
 4. The memoryarchitecture of claim 1, the control interface circuit comprising: apointer control unit coupled to the redundant memory, that generates thepointer address; A fuse box, coupled to the pointer control unitregistering the addresses of the damaged cells of the main memory andoutputting one of the addresses according to the pointer address; acomparable logic unit, coupled to the fuse box comparing the accessaddress with the address output from the fuse box, and generating aredundant selection signal if the address corresponding to the pointeraddress is equal to the access address, if the redundant selectionsignal being activated, the data accessed by the access address from thememory module being read out from the redundant memory.
 5. The memoryarchitecture of claim 4, the control interface circuit comprising a dataselection unit, coupled to the application circuit, the main memory, theredundant memory, the comparable logic unit, if the redundant selectionsignal being activated, the data accessed by the access address from thememory module being read out from the redundant memory, if the redundantselection signal being not activated, the data accessed by the accessaddress from the memory module being read out from the main memory. 6.The memory architecture of claim 5, wherein the data selection unitincludes a multiplexing circuit.
 7. The memory architecture of claim 4,wherein the comparable logic unit includes an assembly of NOR gates. 8.The memory architecture of claim 4, wherein the pointer control unitincrements the pointer address by a step value when the redundantselection signal is set.
 9. The memory architecture of claim 8, whereinthe step value is one.
 10. The memory architecture of claim 4, whereinthe pointer control unit decrements the pointer address by a step valuewhen the redundant selection signal is set.
 11. The memory architectureof claim 8, wherein the step value is one.
 12. The memory architectureof claim 4, wherein the fuse box registers the addresses of the damagedcells of the main memory by cutting off a plurality of fuses in the fusebox by using a laser.
 13. The memory architecture of claim 1, whereinthe main memory is a first-in-first-out memory circuit.
 14. A method forrepairing a serial access memory, the memory module comprising a mainmemory, a redundant memory and a control interface circuit, the controlinterface circuit for storing a plurality of addresses, each of theaddresses corresponding to a damaged memory cell in the main memory,assessing the memory module by an access address; issuing a pointeraddress by the control interface circuit to point to a corresponding oneof the stored addresses stored in the control interface circuit;comparing the address corresponding to the pointer address and theaccess address, if the address corresponding to the pointer address isequal to the access address, data accessed by the access address fromthe memory module being read out from the redundant memory.
 15. Themethod of claim 14, wherein the memory address corresponds to thepointer address issued by the control interface circuit.
 16. The methodof claim 14, wherein if the redundant selection signal is activated, thedata accessed by the access address from the memory module is read outfrom the redundant memory, if the redundant selection signal being notactivated, the data accessed by the access address from the memorymodule is read out from the main memory.
 17. The method of claim 14,wherein the pointer address is incremented by a step value when theredundant selection signal is set.
 18. The method of claim 17, whereinthe step value is one.
 19. The method of claim 14, wherein the pointeraddress is decremented by a step value when the redundant selectionsignal is set.
 20. The method of claim 19, wherein the step value isone.
 21. The method of claim 14, wherein the main memory is afirst-in-first-out memory circuit.